I’m a computer engineer who enjoys automating things and learning across the computing stack. I have experience in developing software as a computer architect/chip design engineer.
Resume
Github
Publications
-
V. Srinivasan, R. Basu Roy Chowdhury, E. Forbes, R. Widialaksono, Z. Zhang, J. Schabel, S. Ku, S. Lipa, E. Rotenberg, W. R. Davis, and P. D. Franzon. H3 (Heterogeneity in 3D): A Logic-on-logic 3D-stacked Heterogeneous Multi-core Processor. Proceedings of the 35th IEEE International Conference on Computer Design (ICCD-35), pp. 145-152, November 2017. pdf
-
R. Widialaksono, R. Basu Roy Chowdhury, Z. Zhang, J. Schabel, S. Lipa, E. Rotenberg, W. R. Davis, and P. D. Franzon. Physical Design of a 3D-stacked Heterogeneous Multi-Core Processor. Proceedings of the 2016 IEEE International 3D Systems Integration Conference (3DIC’16), pp. 1-5, November 2016. pdf slides
-
E. Rotenberg, B. H. Dwiel, E. Forbes, Z. Zhang, R. Widialaksono, R. Basu Roy Chowdhury, N. Tshibangu, S. Lipa, W. R. Davis, and P. D. Franzon. Rationale for a 3D Heterogeneous Multi-core Processor. Proceedings of the 31st IEEE International Conference on Computer Design (ICCD-31), pp. 154-168, October 2013. pdf
-
M Agrawal, K Chakrabarty, R Widialaksono. Reuse-based optimization for prebond and post-bond testing of 3-D-stacked ICs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Link
-
R. Widialaksono, W. Zhao, W. R. Davis and P. Franzon, “Leveraging 3D-IC for on-chip timing uncertainty measurements,” 2014 International 3D Systems Integration Conference (3DIC), Kinsdale, 2014, pp. 1-4, doi: 10.1109/3DIC.2014.7152172. paper poster